The present invention relates to a semiconductor memory device, and in particular, relates to a technology effective when used for a static RAM having a burst mode.
Japanese Unexamined Patent Publication No. 2005-209333 concerns DDR (Double Data Rate) SRAM. The technology described in this publication relates to data input operations in CC mode. Japanese Unexamined Patent Publication No. 2000-298981 provides an example of DRAM that parallel reads multiple bits and serially outputs them for acceleration. A synchronous SRAM is described in 2006 IEEE DIGEST OF TECHNICAL PAPERS pp. 626-628.
[Patent document 1] Japanese Unexamined Patent Publication No. 2005-209333
[Patent document 2] Japanese Unexamined Patent Publication No. 2000-298981
[Non-patent document 1] 2006 IEEE DIGEST OF TECHNICAL PAPERS pp. 626-628